蜂屋 孝太郎
Faculty

学部・大学院

蜂屋 孝太郎

所属 現代ライフ学部 経営学科 講師
現代ライフ学部 経営学科 通信教育課程 講師
環境情報学研究科 環境情報学専攻 講師
最終学歴 早稲田大学大学院 情報生産システム研究科 博士後期課程修了
現在所属している学会 IEEE (The Institute of Electrical and Electronics Engineering)、ACM (Association for Computing Machinery)、電子情報通信学会
学士・修士・博士 博士(工学)
所有資格 ITパスポート
研究の分野 情報学,電気電子工学
主な研究項目 電子回路のシミュレーション・統計解析、シグナルインテグリティ・パワーインテグリティーを考慮したLSI設計手法、アナログ回路の故障シミュレーション・テスト設計自動化
主な研究業績 電源バンプ間抵抗測定によるチップ内電源配線のオープン故障検出手法の提案/DAシンポジウム2020, 情報処理学会, pp. 134-141/単著/2020.09
全学共通科目のオンデマンド教材作成とインタラクティブ環境による学修支援/令和2年度 教育イノベーション大会, 私情協/共著/2020.09
Improving Defect Coverage of Testing Power TSVs by Increasing Sensitivity to TSV Resistance/第33回 回路とシステムワークショップ, 電子情報通信学会, pp. 62-67/単著/2020.08
3D-ICにおける電源TSVの抵抗性オープン故障の検出手法/信学技報, CAS2019-104, 電子情報通信学会, pp.37-41/共著/2020.02
Thermal Placement on PCB of Components including Chip Stacking(査読付き)/2019 Taiwan and Japan Conference on Circuits and Systems, IEEE/共著/2019.08
A Method to Improve Diagnostic Performance of Testing Through Silicon Vias in Power Distribution(査読付き)/2019 Taiwan and Japan Conference on Circuits and Systems, IEEE/共著/2019.08
Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm(査読付き)/The 21th Workshop on Synthesis And System Integration of Mixed Information technologies/共著/2018.03
Resistance Driven Routing Methodology of Power Supply Network for Low Power and Multiple Voltage Design(査読付き)/54th Design Automation Conference, Designer Track/共著/2017.06
Quality Assurance Methodology of Compact MOSFET Models including Variability Effects(査読付き)/48th Design Automation Conference, Designer Track/共著/2011.06
SRAMセル歩留まり解析時間短縮に向けた、モンテカルロ高速化手法の提案(査読付き)/情報処理学会 DAシンポジウム2009 論文集,pp. 193-198/共著/2009.08
Evaluation and Reduction of Simulation Error of Chip-to-Chip Signal Delay(査読付き)/IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 163-166/共著/2005.10
LSI 配線の解析と合成/培風館/共著/2003.12
90nm/GHz クロック・ノードでのインダクタンス考慮設計の実際(査読付き)/情報処理学会 DA シンポジウム 2003 論文集,pp. 19-24/単著/2003.07
インターコネクト・シミュレーション/応用物理,第 72 巻,第 3 号,pp. 339-342,2003/共著/2003.03
Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation/Design, Automation and Test in Europe Conference and Exhibition 2020/共著/2020.03
Thermal placement on PCB of components including 3D ICs/IEICE Electronics Express, Vol. 17, No. 3/共著/2020.01
Thermal Modeling and Simulation of a Smart Wrist-Worn Wearable Device(査読付き)/The 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2019), pp.138-143 /共著/2019.10
Comparison of Diagnostic Performance Metrics for Test Point Selection in Analog Circuits(査読付き)/The 22nd Workshop on Synthesis And System Integration of Mixed Information technologies, pp. 198-203/共著/2019.10
Variability Cancellation to Improve Diagnostic Performance of Testing Through Silicon Vias in Power Distribution Network of 3D-IC(査読付き)/The IEEE International 3D Systems Integration Conference (3DIC 2019), pp. 1-6/共著/2019.10
ESSENCE-Q obtained in routine Japanese public child health check-ups may be a valuable tool in neurodevelopmental screening(査読付き)/Acta Paediatrica, Wiley, pp. 1-10/共著/2019.09
Open Defect Detection of Through Silicon Vias for Structural Power Integrity Test of 3D-ICs(査読付き)/23rd IEEE Workshop on Signal and Power Integrity, pp.1-4/共著/2019.06
Neural Network-Based 3D IC Interconnect Capacitance Extraction/2019 2nd International Conference on Communication Engineering and Technology (ICCET), pp.168-172/共著/2019.04
Optimization of Full-Chip Power Distribution Networks in 3D ICs(査読付き)/IEEE 3rd International Conference on Integrated Circuits and Microsystems, pp.134-138/共著/2018.11
Precise Expression of nm CMOS Variability with Variance/Covariance Statistics on Ids(Vgs)(査読付き)/The 17th Workshop on Synthesis And System Integration of Mixed Information technologies, pp.247-252/共著/2012.03
Fast Methods to Estimate Clock Jitter due to Power Supply Noise(査読付き)/IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E90-A, No. 4, pp.741-747/共著/2007.04
A Method to Derive SSO Design Rule Considering Jitter Constraint(査読付き)/IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 4, pp. 865-872/共著/2006.04
Parallel Iterative Solvers for Sparse Linear Systems in Circuit Simulation(査読付き)/Future Generation Computer Systems vol. 21, No.8, Elsevier Science, Amsterdam, pp. 1275-1284/共著/2005.10
Parallel solution techniques for sparse linear systems in circuit simulation(査読付き)/Scientific Computing in Electrical Engineering, Springer, pp.112-119/共著/2004.10
Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects(査読付き)/IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 4, pp. 841-845/共著/2003.04
Enhancement of Parallelism for Tearing-based Circuit Simulation(査読付き)/Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC) 1997, pp.493-498./共著/1997.01
主な担当授業科目名 ロボット・システム、コンピュータ概論、コンピュータ演習Ⅰ